Constant ON-time controllers are a class of buck regulators that use the output voltage ripple to initiate an ON-time whenever the output voltage falls below the reference voltage. The ON-time is terminated (generating an ON-time pulse) by circuitry in response to other conditions (e.g., level of regulator input). During the ON-time pulse, energy is supplied directly from the regulator input to the output via an electronic switching device. Likewise, when the ON-time pulse has terminated stored energy from the regulator input is supplied to the output. Most constant ON-time regulators include circuits to adjust the ON-time pulse duration as a function of the input and output voltages, thus resulting in an almost constant frequency as the duty cycle changes. The output voltage ripple is determined to a large extent by the ripple current in the energy storage inductor flowing through the output capacitor's equivalent series resistance (ESR). In applications that require low voltage ripple, the ESR must be very small. This creates two problems for constant ON-time controllers, stability and susceptibility to noise. Some circuits use techniques that supplement the ESR generated ripple with a voltage ramp. These voltage ramps minimize the susceptibility of the controller to noise and thus substantially reduce jitter.
FIG. 1 is a circuit diagram of circuit 100 illustrating a buck regulator and a typical constant ON-time controller. The voltage output (Vout) 116 is set by the duty cycle which is defined as the ratio of ON-time of the high side field effect transistor (FET) 107 to the total switching period. In steady state, Vout 116 is close to the same value as Vref 117. Whenever Vout 116 drops below Vref 117, output 130 of comparator 108 sets latch 109. Gate drivers 100 turn ON FET 107 thereby charging inductor (L) 104 and delivering current to the load (not shown) coupled to the Vout 116. Vout 116 will begin increasing and when it exceeds Vref 117 output 130 of comparator 108 transitions to logic zero and removes the set from latch 109. Latch 109 remains set until the voltage 118 across capacitor (C) 111 exceeds Vref 117. At this time, output 131 of comparator 110 resets latch 109 and gate drivers 100 turn OFF FET 107 and turn ON FET 106. When latch 109 is reset, latch 109 output 133 turns ON FET 112 discharging C 111 thereby causing comparator output 131 to go to logic zero removing the reset to latch 109. One-shot circuit 114 comprising R 113, C 111, FET 112, comparator 110, and latch 109 generates the ON-time for circuit 100. Since at any one value of Vin 115, the ON-time of circuit 100 is dependent only on Vref 117 and the time constant of R 113 and C 112, the ON-time is considered “constant”. The energy stored in inductor (L) 104 causes current to continue to flow to a load (not shown) coupled to Vout 116. Catch diode (D) 105 insures that the current in L 104 is not interrupted thus minimizing transients during switching. Resistor R 103 may be used to sense the current to Vout 116.
The time FET 107 is ON (ON-time) is a function of both Vin 115 and Vref 117. As Vin 115 rises, the ON-time will be shorter since C 111 charges faster. If Vref 117 is increased, C 111 has to charge to a higher voltage to trip comparator 110, which also results in a longer ON-time. Thus, the circuitry adjusts the ON-time to minimize the frequency changes (as determined by the time between pulses) that would otherwise result from changes in Vin 115 and Vout 116. To increase the current in L 104 in response to a step change in the load (not shown) coupled to Vout 116, the control loop generates more ON pulses per unit time. To decrease the current in L 104, the control loop generates fewer pulses per unit time. Therefore, during transient load steps the frequency is not constant.
The advantage of constant ON-time controllers is response time. Unlike current mode and voltage mode buck controllers, constant ON-time controllers require no error amplifier and thus their control loop starts responding instantaneously to transient load steps. A buck regulator using a constant ON-time controller has a transient response that is limited only by the energy storage inductor (e.g., L 104) and the input voltage (e.g., Vin 115). These two variables substantially determine how fast the current in L 104 changes in response to a load step. Another advantage of the constant ON-time controller is that the control loop normally does not require any compensation.
The disadvantage of constant ON-time controllers only becomes apparent when the ESR 102 of C 101 becomes very small. ESR 102 is the real part of the complex impedance of C 101. In this situation, the voltage ripple on Vout 116 may be in the range of 15 millivolt (mv) or less and voltage comparator 108 may trip on switching noise coupled into its inputs. When voltage comparator 108 trips on noise, there are resulting variations in the ON-time, which are referred to as “jitter”. The jitter is not a sign of instability, but rather it has the effect of generating uncontrolled voltage ripple on Vout 116 and is therefore undesirable.
Stability is the major problem with constant ON-time controllers in applications using low ESR capacitors. L 104 and C 101 make up an LC filter in the output stage that introduces a double “pole” (goes to an infinite value) in the filter transfer function with the poles located at the LC resonance frequency. ESR 102 introduces a “zero” (goes to a zero value) at the frequency were the impedance of C 101 is equal to the value of ESR 102. This zero needs to be introduced into the control loop at a frequency well before the unity gain crossover frequency or the control loop will be unstable. As the ESR/capacitance ratio becomes smaller, the associated zero occurs at a higher frequency. Eventually too much phase shift occurs in the loop response and the control loop becomes unstable. An unstable control loop may over react to a transient load step and cause the current in L 104 to overshoot resulting in excessive ringing. Large output capacitors (e.g., C 101) are generally fabricated by paralleling many smaller capacitors. Individual small ceramic capacitors have a very low ESR/capacitance ratio. If a significant number of these low ESR ceramic capacitors are used (paralleled) to make C 101, the control loop may become unstable. This is particularly true in low power applications where all the capacitors making up C 101 may be ceramic and also in high current applications where many ceramic capacitors are needed to achieve the necessary capacitance for the desired transient response.
Voltage ramps have been used to combat the noise susceptibility problem for constant ON-time controllers. A simple constant ON-time buck converter using a voltage ramp in this manner is shown as circuit 200 in FIG. 2. In this example, the feedback (sensing Vout 216) is taken upstream from Vout 116 (negative input to comparator 208). Circuit 200 has elements similar to circuit 100 in FIG. 1. The explanations concerning circuit elements of circuit 100 that are included in circuit 200 are repeated so that reference will not have to be made back to FIG. 1.
Circuit 200 is a typical constant ON-time controller with some modifications. Vout 216 is set by the duty cycle that is defined as the ratio of ON-time of the high side FET 207 to the total switching period. In steady state, Vout 216 has nearly the same value as Vref 217. Whenever Vout 216 drops below the reference voltage Vref 217, output 230 of comparator 208 sets latch 209 and gate drivers 200 turn ON FET 207 charging L 204 and delivering current to the load (not shown) coupled to the Vout 216. Vout 216 then starts increasing and when it exceeds Vref 217, output 230 of comparator 208 transitions to logic zero and removes the set from latch 209. Latch 209 remains set until the voltage 218 across C 211 exceeds Vref 217. At this time, output 231 of comparator 210 resets latch 209 and gate driver 200 turns OFF FET 207 and turns ON FET 206. When latch 209 is reset, latch output 233 turns ON FET 212 which discharges C 211 causing comparator output 231 to go to logic zero removing the reset to latch 209. One-shot circuit 214 comprising R 213, C 211, FET 212, comparator 210, and latch 209 generates the ON-time for circuit 200. Since at any one value of Vin 215 the ON-time of circuit 200 is dependent only on Vref 217 and the time constant of R 213 and C 212, the ON-time is considered “constant”. The energy stored in L 204 causes the current to continue to flow to Vout 216. D 205 insures current in L 204 is not interrupted to minimize transients during switching. Resistor R 203 may be used to sense the current to Vout 216.
The ON-time (time FET 207 is ON) is a function of both Vin 215 and the Vref 217. As Vin 215 rises, the ON-time will be shorter since C 211 charges faster. If Vref 217 is increased, C 211 has to charge to a higher voltage to trip the comparator 210, also resulting in a longer ON-time. Thus, the circuitry adjusts the ON-time to minimize the frequency changes (as determined by the time between pulses) that would otherwise result from changes in Vin 215 and Vout 216. To increase the current in L 204 in response to a step change in the load (not shown) coupled to Vout 216; the control loop generates more ON pulses per unit time. To decrease the current in L 204, the control loop generates fewer pulses per unit time. Therefore, during transient load steps the frequency is not constant. The PCB trace resistance Rtrace 215 increases the effective equivalent series resistance (ESR) seen by the control loop. The effective ESR as seen by the control loop is Rtrace 218 plus ESR 202 while the ESR of capacitor C 201 relative to its ability to smooth the output ripple remains the same. However, taking the feedback upstream adds “droop” to Vout 216 as the drop across Rtrace 218 is a function of load current.
Circuit 300 is another constant ON-time buck regulator where a ramp is introduced in the feedback loop to improve noise rejection. Circuit 300 has elements similar to circuit 100 in FIG. 1. The explanations concerning circuit elements of circuit 100 included in circuit 300 are repeated so that reference will not have to be made back to FIG. 1.
Circuit 300 is a constant ON-time buck converter with some modifications. Vout 316 is set by the duty cycle that is defined as the ratio of ON-time of the high side FET 307 to the total switching period. In steady state, Vout 316 has nearly the same value as Vref 317. Whenever Vout 316 drops below the reference voltage Vref 317, output 330 of comparator 308 sets latch 309 and gate drivers 300 turn ON FET 307 charging L 304 and delivering current to the load (not shown) coupled to the Vout 316. Vout 316 then starts increasing and when it exceeds Vref 317, output 330 transitions to logic zero and removes the set from latch 309. Latch 309 remains set until the voltage 318 across C 311 exceeds Vref 317. At this time, output 331 of comparator 310 resets latch 309 and gate driver 300 turns OFF FET 307 and turns ON FET 306. When latch 309 is reset, latch output 333 turns ON FET 312 which discharges C 311 causing comparator output 331 to go to logic zero removing the reset to latch 309. One-shot circuit 314 comprising R 313, C 311, FET 312, comparator 310, and latch 309 generates the ON-time for circuit 300. Since at any one value of Vin 315 the ON-time of circuit 300 is dependent only on Vref 317 and the time constant of R 313 and C 312, the ON-time is considered “constant”. The energy stored in L 304 causes the current to continue to flow to Vout 316. D 305 insures current in L 304 is not interrupted to minimize transients during switching. The energy stored in L 304 causes the current to continue to flow to Vout 316. Catch diode (D) 305 insures current in L 304 is not interrupted to minimize transients during switching.
The ON-time (time FET 307 is ON) is a function of both Vin 315 and the Vref 317. As Vin 315 rises, the ON-time will be shorter since C 311 charges faster. If Vref 317 is increased, C 311 has to charge to a higher voltage to trip the comparator 310, also resulting in a longer ON-time. Thus, the circuitry adjusts the ON-time to minimize the frequency changes (as determined by the time between pulses) that would otherwise result from changes in Vin 315 and Vout 316. To increase the current in L 304 in response to a step change in the load (not shown) coupled to Vout 316; the control loop generates more ON pulses per unit time. To decrease the current in L 304, the control loop generates fewer pulses per unit time. Therefore, during transient load steps the frequency is not constant.
In circuit 300, the voltage across sense resistor R 303 is AC coupled via C 337 and R 318 to sensed Vout 336 to generate the input to comparator 308. Again this increases the ripple as seen by the control loop without increasing the ripple on Vout 316.
Circuit 400 is another constant ON-time buck regulator where a ramp is introduced in the feedback loop to improve noise rejection. Circuit 400 has elements similar to circuit 100 in FIG. 1. The explanations concerning circuit elements of circuit 100 included in circuit 400 are repeated so that reference will not have to be made back to FIG. 1.
Circuit 400 is a typical constant ON-time controller with some modifications. Vout 416 is set by the duty cycle that is defined as the ratio of ON-time of the high side FET 407 to the total switching period. In steady state, Vout 416 has nearly the same value as Vref 417. Whenever Vout 416 drops below the reference voltage Vref 417, output 430 of comparator 408 sets latch 409 and gate drivers 400 turn ON FET 407 charging L 404 and delivering current to the load (not shown) coupled to the Vout 416. Vout 416 then starts increasing and when it exceeds Vref 417, output 430 transitions to logic zero and removes the set from latch 409. Latch 409 remains set until the voltage 418 across C 411 exceeds Vref 417. At this time, output 431 of comparator 410 resets latch 409 and gate driver 400 turns OFF FET 407 and turns ON FET 406. When latch 409 is reset, latch output 433 turns ON FET 412 which discharges C 411 causing comparator output 431 to go to logic zero removing the reset to latch 409. One-shot circuit 414 comprising R 413, C 411, FET 412, comparator 410, and latch 409 generates the ON-time for circuit 400. Since at any one value of Vin 415 the ON-time of circuit 400 is dependent only on Vref 417 and the time constant of R 413 and C 412, the ON-time is considered “constant”. The energy stored in L 404 causes the current to continue to flow to Vout 416. D 405 insures current in L 404 is not interrupted to minimize transients during switching. Resistor R 403 may be used to sense the current to Vout 416.
The ON-time (time FET 407 is ON) is a function of both Vin 415 and the Vref 417. As Vin 415 rises, the ON-time will be shorter since C 411 charges faster. If Vref 417 is increased, C 411 has to charge to a higher voltage to trip the comparator 410, also resulting in a longer ON-time. Thus, the circuitry adjusts the ON-time to minimize the frequency changes (as determined by the time between pulses) that would otherwise result from changes in Vin 415 and Vout 416. To increase the current in L 404 in response to a step change in the load (not shown) coupled to Vout 416, the control loop generates more ON pulses per unit time. To decrease the current in L 404, the control loop generates fewer pulses per unit time. Therefore, during transient load steps the frequency is not constant.
Circuit 400 is a more elaborate circuit using a ramp. In circuit 400, a voltage ramp is artificially generated and added directly to the feedback while a slow, precision transconductance amplifier (GMA) 428 corrects for the DC errors introduced by the voltage ramp. A GMA (e.g., GMA 428) produces a current output in response to an input voltage times a gain factor (e.g., Gm). When gate drivers 419 turn ON the low side FET 406, the same signal turns ON FET 421 enabling current source 420 to begin charging C 422. This voltage ramp is impressed across R 424 using operational amplifier (Opamp) 423 and FET 425 thus producing a current ramp (IR) 450. IR 450 is replicated as IRM 451 with current mirror FETs 426 and 427. IR 451 flows in the drain of FET 427 and is used to supplement the output voltage ripple by adding a ripple voltage equal to IR 450 times R 418. IR 450 has a slope determined by the value of current source 420 and the capacitance value of C 422. IR 450 is abruptly terminated when FET 421 turns OFF in response to FET 406 turning OFF, C 422 then discharges through R 452.
A DC correction current, equal to the difference between Vout 416 and Vref 417 times the transconductance Gm, is supplied from the GMA 428. Resistors R 430 and R 431 charge and discharge capacitor C 429 with a current proportional to the difference in Vref 417 and Vout 416. The voltage across C 429 is the integral of this current producing a “filtered” voltage at the inputs to GMA 428 proportional to the difference in Vref 417 and Vout 416. GMA 428 produces an output current (either positive or negative) that slowly compensates for the offset produced by the ramp current IR 451 as long as there is an offset between Vout 416 and Vref 417. The total system offset is set by any inherent offset of GMA 428.
GMA 428 may be implemented as a digital circuit (e.g., comprising an up/down counter, oscillator, and DAC current source; these elements are not shown). The bandwidth of GMA amplifier 428 should be two orders of magnitude below the switching frequency. In a digital implementation of GMA 428, the bandwidth may be adjusted by changing the clock frequency to an up/down counter. This allows for an adaptive bandwidth control. The bandwidth is increased if the difference between Vout 416 and Vref 417 is great. The other desirable feature resulting from implementing GMA 428 as a digital circuit is that its response may be made slow enough that it does not react to transient load steps until the transient step is complete and a new steady state condition is established. While adding an artificially generated ramp has advantages, designing GMA 428 to have the desired bandwidth characteristics and dealing with offsets presents difficulties.
The preceding discussion has shown the improvements and the problems that result from using a compensating ramp in constant ON-time controllers for buck regulators. To overcome the problems, there is a need for circuitry to enable a constant ON-time controller to use real or artificial generated ramps when the ESR of the filter capacitor is low while overcoming the disadvantages of offsets requiring difficult to design offset compensation.